Overview of Orora Solutions

Orora software products Arana and Arsyn are used in the design, implementation, validation and debugging stages of analog and radio frequency integrated circuits. They are designed to be used by analog/RF designers, regardless of experience level, to efficiently implement leading-edge, performance-driven designs as well as to facilitate rapid design reuse.

Product flowchart

  1. Automated Baseband Analog Design and Reuse Solution

    Arana and Arsyn provides the complete design solution to baseband analog circuit design.

  2. Automated RF Design and Reuse Solution

    With Cadence Design Environment, Arana and Arsyn provide the first equation-driven design and analysis solution for RF integrated circuits. Instead of numeric simulators, Arana can derive automatically analytic equations for gain (S11, S12, S21, S22), HD2, IP3, noise figure, input/output impedance, isolation, fabability factors, in terms of design parameters. With these equations, design tradeoff and whatif analysis can be performed and visualized in real time. Further, Arsyn find designs with the best possible tradeoff among all the specifications and constraints.

  3. Mixed-Signal Full-Chip Verification Solution

    Design verification before tape out is critical to eliminate and reduce the risk of silicon re-spins, and therefore save the cost and reduce the time to market. While a range of technologies exist for the verification of digital circuit implementation, the only tool available for analog design verification is transistor-level SPICE circuit simulation. With over than 50% chip designs are mixed-signal (analog and digital), the only viable solution to complete mixed-signal systems-on-chip verification is multi-level mixed analog and digital circuit simulators such as recently introduced AMS designers by Cadence, NanoSim by Synopsys and AMS Advance by Mentor Graphics. Unfortunately, analog simulation is extremely slow and often is the bottleneck of the entire mixed-signal simulation. Orora tools Arana and Arsyn enable the creation of silicon-accurate behavioral models.

  4. Silicon Debugging Solution

    According to a recent industry survey, more than half of chip implementations require silicon re-spins. Most analog/RF circuit implementation requires at least one additional silicon spin. A considerable amount of designers' time has to be spent on debugging what is wrong with the chip implementation. It is not un-common that one design can take more than fix months and multiple test setups to debug why certain specifications are not met (while in this case, simulation often indicates that the specifications are met). Seamlessly integrated in circuit design environments, Arana can be used to reduce greatly the silicon debugging time for analog and RF circuits.