Rockwell Scientific Doubles 4Gsps ADC Product Yield Using Orora’s Arsyn Analog Design Tool
Redmond, WA, March 18, 2006 — Orora Design Technologies, Inc., an emerging leader in analog design automation software, today announced that Rockwell Scientific has applied Orora’s Arsyn Circuit Synthesis Platform to a 4Gsps ADC ASIC design, which achieved 5 times reduction in design cycle time, doubled product performance yield, and improved overall performance by 15%. This silicon-proven success was highlighted at the 2006 DARPA Symposium on Microelectronics, held here in San Francisco, February 12, 2006.
“This work has culminated out of 3 generations of development at Rockwell of advanced multi-Gsps ADC’s under the DARPA Advanced Digital Receiver Technology (ADRT) program. We believe Orora’s tools provide new opportunities for demonstrating better ADC performance.” noted Dr. M-J Choe, Manager of Mixed-Signal Design at Rockwell. M-J Choe is a renowned analog expert with 2 papers describing this work at the 2005 IEEE International Solid-State Circuit Conference.
The ADC development consisted of a three month evaluation using two design groups, one consisting of senior Rockwell designers using traditional Cadence tools with their developed optimization scripts, and the other consisting of a student intern supervised by a senior Rockwell designer using the Arsyn Circuit Synthesis Platform. Two designs were laid out side by side and fabricated and then tested.
The results showed that the design using Arsyn not only had better performance (15% overall), but also had much less performance variability across parts. Yield test results showed the design using Arsyn optimization doubled the performance yield versus the standard design techniques.
In his presentation to DARPA Symposium on Microelectronics, Dr. Dennis Healy, DARPA Program Manager, pointed out “This success has clearly demonstrated that the huge potential of design for manufacturability using the science of modeling and optimization”.
